(a) Field of the Invention
The invention relates to an integrated circuit anti-interference outline structure, and more particularly, to an anti-interference outline suitable for disposing within an integrated circuit; wherein two metal strips provided at the surface of the integrated circuit are applied with a positive voltage and connected to GND, respectively, so as to generate a significant parasitic capacitance at poly layers thereof in between, and to further control noises thereof within acceptable ranges; and a P-type substrate therein is provided with a deep N-well for connecting with an N-terminal of an N-well layer, so as to produce a positive voltage zone having a large area such that noises are disallowed to pass through and are instead overflowed through a ground terminal having a lower voltage, thereby shielding the integrated circuit from invasions and leaks of electromagnetic waves.
(b) Description of the Prior Art
Accompanied with advancement of technology, products that we use become better in quality and precision, and therefore it is essential that the integrated circuits contained therein have more exact designs. However, in the internal design of an integrated circuit, the structure therein is made up of electronic circuit layouts, and some noises that interfere with one another are inevitably produced. The phenomenon occurs even more frequently in an integrated circuit for that the integrated circuit is consisted of a great quantity of circuits, and hence it is important to minimize the interference signals. In a prior art, housing shielding and aperture shielding are generally used in combination for screening external noise interferences. However, such method is incapable of entirely eliminating external noise interferences, and only succeeds in isolating external noises but fails to isolate noise interferences at the interior thereof. Also, the internal structure of a prior integrated circuit lacks countermeasures and designs for resolving the aforesaid difficulty; and as closer the circuits in the integrated circuit get with one another, the more likely the noises generated will stray along the circuits, thus seriously affecting stability and quality of the integrated circuit.
In the view of the above shortcomings, the inventor has a patent application Ser. No. 10/189,495, “Domestic Priority Data as Claimed by Applicant”, wherein an integrated circuit anti-interference outline structure is provided for solving external and internal noise interferences, and two metal strips and PNP structures of varied amounts are employed to produce parasitic capacitance for isolating external noises, thereby forcing the internal noise currents to overflow through a ground terminal using a positive voltage zone produced, as well as preventing invasions of external noises and interferences of internal noises.